1. Field of the Invention
The present invention relates to a debugging system for a computer system. More specifically, the invention relates to a debugging system adapted to a computer system employing a microprocessor incorporating a virtual storage management function for converting a virtual address into a real address.
2. Description of the Related Art
In the modern computer systems, there are several types of virtual address management systems for realizing required greater address space. One of the typical virtual address systems has been known as a paging system. In the paging system, a virtual address and a real address are divided into the same size unit which is referred to as a "page". Normally, each page may have a capacity in the order of 4K bytes. The upper address of each address is used to identify of a page number. Assuming the page number of the virtual address is n, the page number n in question is mapped in the page number N of the corresponding real address.
For instance, the virtual address space is greater than the real address as such when the virtual address is 4 G (2.sup.32) bytes, the real address space is 16M (2.sup.6) bytes. Therefore, by assigning the one page of the real address to a plurality of pages of the virtual address, corelation between the virtual address space and the real address space is established. The mechanism for establishing a correlation between the virtual address space and the real address space is a virtual storage management mechanism.
The virtual storage management system has been typically in a form of a separate device out of a microprocessor outputting the address bus as the virtual address for large device scale. In such a system, for significant delay between the devices, loss factor in address conversion becomes large to causes degradation of performance of the system.
On the other hand, in the recent years, for development of the semiconductor integration technologies, it becomes typical to incorporate such virtual storage management mechanism within the microprocessor main frame. Therefore, the virtual address which is originally unnecessary as external operation of the microprocessor, is not output from the microprocessor. In the system employing the microprocessor incorporating the virtual storage management mechanism, a debugging system is normally employed for debugging the system.
In general, when a programmer prepares a program, the program is described only using the virtual address. Accordingly, at the verification stage by the programmer for verifying the program operation, analysis of error, enhancement of the performance and so forth, it is not possible to efficiently perform the operation by using only output of the microprocessor corresponding to the real address. Therefore, in order to improve efficiency, the debugging operation is normally performed with employing the debugging system and using the virtual addresses which are not output from the microprocessor.
Methods for performing debugging operation include a tracing method for tracing the operation expected by the program in order and a trapping method for verifying if the program will execute an expected operation when a specific address is accessed.
In the tracing method, a bus cycle issued by the microprocessor is monitored for checking whether the program is executed with an expected sequence and whether correct data transmission and reception is performed, according to an elapsed time. At this time, the contents to be monitored are a kind of bus cycle, output address and transferred read/write data and so forth.
In the trapping method, the bus cycle issued by the microprocessor is monitored and providing a program for causing branching upon access of a specific address which is preliminarily set by the programmer and outputting of an internal condition to be verified to the branching destination, for checking whether the preliminarily expected process is executed or not. At this time, the contents to be checked includes information of an internal cache which can be output, data of a general purpose register, data of a microprocessor control register, a resuming swapped by the microprocessor for resumption of an interrupted process by trapping and so forth.
As a method for realizing such a debugging system, there is a method, in which a special microprocessor (hereinafter referred to as "debugging processor") for outputting the virtual address instead of outputting of the real address. FIG. 6 is a block diagram showing a construction of the debugging system employing such a debugging processor. In FIG. 6, the debugging system includes a microprocessor 601, a debugging processor 602, a memory device 603 and a bus monitoring device 604.
The microprocessor 601 is connected to the memory device 603 via the address bus 6005 and the data bus 6006, and forms one microprocessor application system.
To the address bus 6005, the real address is output from the microprocessor 601. In the debugging processor 602 which uses the data bus 6006 in common with the microprocessor, does not drive the address bus 6005 during data read/write cycle. On the other hand, the debugging processor 602 generally performs the same operation as the microprocessor except for outputting of the virtual address to a virtual address bus 6010 as the address. Namely, the microprocessor 601 and the debugging processor 602 operate to perform the same operation at the same time with complete synchronization therebetween.
In the bus monitoring device 604, sampling is performed for the address on the virtual address bus 6010 and the signal 6001 indicative of the kind of data bus cycle of the data bus 6006, the read/write signal 6002, the data access signal 6003 and the bus cycle start signal 6004.
FIG. 7 shows a construction of a trace circuit included within the bus monitoring device 604. The trace circuit comprises a trace memory device 701, a counter 714 and an AND circuit 702. In this trace circuit, the signal 6001 indicative of the kind of the kind of the data access of the virtual address bus 6010, the read/write signal 6002, the bus cycle start signal 6004, the read/write data of the data bus 6006 are sampled with a bus cycle clock 7011, to which the read/write data of the data bus 6006 is input via an inverter 703, per each clock and stored in the trace memory device 701. It should be appreciated that the reference number 7012 is a trace start signal.
FIG. 8 shows a construction of a trap circuit to be incorporated in the bus monitoring device 604. The trap circuit comprises a trap address register 801, a comparator 802, and a flip-flop 803. In the trap address register 801, the virtual address for trapping is set with a trap address 8001 and a trap set signal 8002. The set virtual address and the virtual address bus 6010 are compared in the comparator 802. When both virtual addresses matches, a matching signal 8005 is output and input to the flip flop 803. From the flip flop 803, s trap demand signal is output on the basis of a clock 6011 input via an inverter 804. The trap demand signal 8007 is input to the microprocessor 601 and the debugging processor 602. By this, the trapping function of the bus monitoring device 604 can be realized.
In the above-mentioned conventional debugging system, since the real address is output from the microprocessor, in which the debugging system is incorporated, it is not possible to monitor the bus cycle in the virtual address.
On the other hand, in the case where the debugging processor is provided in parallel to the microprocessor in order to enable monitoring of the bus cycle in the virtual address, extra device having substantially the same function, construction to the microprocessor becomes necessary. Therefore, it causes high cost in construction.
Furthermore, due to tolerance in manufacturing of the devices, it is very difficult to establish complete matching between the microprocessor and the debugging processing in the set-up period and delay period and so forth.
In particularly to the second problem, when the debugging system is operated at a high frequency range, such as 33 MHz, it becomes inherently necessary to provide a debugging processor which can establish good matching with the microprocessor. When this condition is not satisfied, it becomes impossible to establish synchronization between the microprocessor and the debugging processor and impossible to execute the debugging process by the debugging system.